High-Throughput Looping in Stream Processors Using Self-Timed Architectures

Special-purpose stream-processing systems are becoming increasingly popular due to the demands of multimedia applications, digital signal processing, and cryptography. In stream-processing systems, algorithms are typically implemented as a series of hardware stages. Each hardware stage receives the data stream from the previous stage and, after processing, sends the new data stream to the next stage. The focus of this work is on application-specific stream processors, rather than general-purpose programmable devices. The presence of conditional constructs (e.g., conditional branches, loops, etc.) in an algorithm poses a significant challenge to creating efficient stream processors. This difficulty is further exacerbated if the control constructs are data-dependent, e.g., a loop with a variable iteration count. Past work by Kapasi, Dally et al. [2] only addressed the problems related to conditional branches, but did not address the critical challenge of pipelining loops. Our work addresses this key challenge by providing a comprehensive approach to handle various types of loop constructs, thereby extending the set of algorithms that can be efficiently implemented as stream processors. We target not only fixed-iteration “for” loops, but also variable-iteration (e.g., data-dependent) “while” loops. Furthermore, our approach extends to nested as well as unrolled loops. Our method is applicable to those algorithms that iterate several times on the same data set (e.g., iterative ODE solvers). Our strategy is to allow the body of the loop to operate on multiple data sets concurrently. This requires extra storage to allow each data set to maintain a distinct copy of its algorithmic state. A key contribution is the design of an efficient loop control block that supervises loop activity, and ensures that the loop is operating at maximum achievable throughput, i.e., neither sparsely occupied nor congested. Our implementation architecture is based on asynchronous or self-timed pipelines and rings, which offer several benefits for the design of stream processors. Self-timed circuits are more energy-efficient because they consume little energy when idle. A self-timed approach can also reduce design effort considerably through greater design modularity.